FIG. 1, shows a simplified schematic cross-section of a portion of an integrated circuit (IC) chip with a diffused drain power transistor, illustrating a typical n-type Laterally Diffused drain Metal Oxide Silicon (n-LDMOS) power transistor structure in silicon substrate 100, of the prior art, where on a p-substrate, an N-tub and a N-buried layer is formed by methods well known in the art. The structure 100, typically has an inter-metal dielectric (IMD) layer or film 105, with drain 101, in an N-well, source 102, gate 103, and extended drain 110. These power transistors use an extended drain 110, with low doping concentration to prevent the inversion layer, which is initiated at drain contact 101, when power is off, from extending into the gate region 103. It is well known that the low doping and extended drain region 110, is the main source of high Rds-on in power transistors.
The typical circuit layout for power transistors, as illustrated in FIG. 1, is to linearly lay these power transistors in a linear array with parallel circuit connections as more clearly shown in FIG. 3A, of various components of an IC contributing to R-on. Furthermore, FIG. 3B shows equivalent circuits of power transistors laid out in area array form, while FIG. 3C is an enlarged view of the equivalent circuits as shown in FIG. 3B. This linear array layout of FIG. 3A, is generally used by designers to keep the interconnect resistance at the minimum and to keep the temperature low and uniform. Accordingly, a semiconductor integrated circuit for high voltage application is characterized by a large circuit area for its lateral organization of power transistors, and these individual transistors themselves are relatively large, being comprised of a low-doped extended drain area required for high blocking voltages.
In addition to larger silicon area, which implies a higher product cost, the large device area also limits the electric current level that can be used, particularly because of the “hot-spot” generation.
In power devices, a parameter of importance is “R-on” which is broadly comprised of two components, Rds-on and Rint. The Rds-on is characterized by the given semiconductor process technology node, device structure and operating conditions including device junction temperature. For a group of power transistors in a given technology node and device structure, configured in a given manner and operating at a given gate voltage Vgs and device junction temperature Tj, the Rds-on is mostly fixed. The Rint on the other hand is characterized by the metal interconnect resistance arising from metal traces and vias between the bond wire and source/drain contacts as shown in FIG. 3A. The Rint also comprises the bond wire resistance and the package resistance arising from leads, traces and vias, depending upon the package type.
To optimize circuit performance, circuit designers usually consider lowering the “specific resistance,” Rsp, of the power transistor layout. The specific resistance, Rsp, is defined as a product of Rds-on and the power device area:Rsp=Rds-on*Device Area.
Rds-on is more or less fixed as mentioned above, the interconnect metal resistance component of Rint, and thereby the value of Rint, can be reduced by utilizing a thick low resistivity metal interconnect, referred to hereinafter as “Power Metal.” This is because:R-on=Rds-on+Rint, which is the reduction of Rint by the use of power metal, which reduces R-on.
FIG. 2, shows reduction of R-on with increasing thickness of Power Metal or PowerM (i.e., decreasing interconnect resistance). However, for a given application, the R-on is a fixed quantity, hence reduction of Rint by the use of power metal, allows one to increase the Rds-on; that allows reduced device area for a given Rsp.
Thus the main application of thick low resistivity power metal on power devices has been to shrink the device area for cost benefit. On the other hand, one may choose to use the Power Metal and keep the device area same and allow a higher Rds-on. Because the Rds-on is a direct function of device junction temperature, the use of Power Metal will thereby allow a higher junction temperature, Tj. Power transistors normally operate at about 150 C maximum junction temperature, however, with the use of Power Metal, transistors can thus operate up to 200 C junction temperature.
Applications requiring service at high temperature, such as, for example, alternator controller, under the hood applications, transmission control or brakes in automobile, to name a few, require the device to function at junction temperatures in the range of 150 C to 200 C. Such applications also require a high current, 4 A to 10 A with peak current going up to 30 A. A thick aluminum wire (wire diameter from about 8 mil to about 20 mil) is generally used for wire bonding on chip for its high current carrying capability (about 8 A to about 40 A), with mechanical strength to sustain high amplitude vibration and low cost. For such applications the three preferred choices for power metal are Copper, Aluminum and Gold. Silver is another choice but it suffers from strong atmospheric corrosion susceptibility. It should be noted that the required thickness of power metal is in the range of about 8 um to about 35 um to play a beneficial role in power transistors. Presently, a metal film of such thickness can only be deposited by electroplating technique. Because aluminum cannot be electroplated, the choice of power metal is limited to either Copper or Gold. Both of these metals are metallurgically incompatible with Aluminum that is used for wire bond as mentioned above. Basically, Aluminum forms intermetallic compounds with either Copper or Gold giving reliability problems in temperature storage test, especially above 150 C. For this reason the copper metal interconnects are usually coated with Nickel followed by a thin layer of Gold or Palladium/Gold.
Another significant problem in power devices is “hot spots.” Because of the additional resistance coming from the extended drain 110, power transistors dissipate more energy, so the driver region of the IC chip becomes the hottest region, called “hot spots.” Temperature in hot spots, depending upon the number of power transistors in a given array, the array layout, operating frequency and duty cycle, and leakage current, can rise up to 350 C. These localized hot spots that are significantly above the average die or chip temperature, limit the IC's performance and reliability. However, power metal provides an added advantage of reducing the intensity of a hot spot by spreading the heat. Accordingly, a power metal with high thermal conductivity is desired which is also thermally stable with Aluminum interconnect and bond wire at these hot spot temperatures.
The use of thick, low resistivity Power Metal interconnects in power devices has been explored in the prior art. For example, U.S. Pat. No. 7,132,726 (Rueb et al.), the disclosure of which is incorporated herein by reference, discloses a method to provide a thick aluminum pattern over power devices and a thin aluminum interconnect for a fine line pattern in logic circuit. First a 3 um thick aluminum interconnect is defined by wet etch process in power transistor area of the device die, followed by 0.8 um thick aluminum fine line pattern defined by Reactive Ion Etch (RIE) process. Rueb et al. disclose that at least about 10 um thick copper is required for R-on reduction to be beneficial. This translates to about 16 um thick Ti/Al-0.5% Cu interconnect metal thickness. To define interconnect metal pattern with metal thickness above about 3 um, the techniques such as wet etch, Reactive Ion Etch, Damascene or Metal Lift-off are not applicable in the required resolution range of less than 10 um. For metal thickness above 3 um, the usual metal interconnect formation technique involves electroplating into a negative pattern of interconnects defined by either positive or negative photoresist. There is no known electroplating technique for aluminum, hence, Rueb et al.'s teaching does not provide solutions to overcome the prior art problems.
U.S. Pat. No. 6,372,586 (Efland et al.), the disclosure of which is incorporated herein by reference, discloses a method to overlay a thick copper layer making contact to at least a part of the last aluminum metal layer of an IC device through the passivation layer. Efland uses the industry standard “electroplating through negative mask pattern” technique to deposit up to 20 um thick copper with TiW barrier.
U.S. Pat. No. 7,045,903 (Efland et al.), the disclosure of which is incorporated herein by reference, discloses an improved TiW/Cu structure which is obtained by electroplating Nickel and gold layers on top of copper. This structure provides superior gold wire-bond reliability. However, this structure has several shortcomings for high temperature high current applications, which require a large diameter aluminum wire bonding, such as, for example, at about 175 C the pure electroplated nickel diffuses almost through the copper layer underneath in about 100 hours, thereby substantially increasing the resistivity of the thick copper interconnect. Furthermore, the TiW/Cu or TiW/Cu/Ni/Au is not compatible with thick aluminum wire-bonding as aluminum and copper or gold (if gold is more than 1000 A thick) react to form CuAl2 or AuAl2 inter-metallic compound which is well known in the industry for poor reliability, especially above 150 C, due to Kirkendall void formation leading to Open-Circuit. Electroplating less than 3000 A thick gold is a non-manufacturable process because of high plating rate in the industry standard cyanide bath used for gold plating. One of the most serious shortcoming of these Power Metal structures is the unprotected copper sidewall, especially, with the presence of humidity, temperature and electrical bias, copper atoms migrate from the unprotected copper sidewalls causing electrical shorting between adjacent interconnect lines. With industry standard Highly Accelerated Stress Test (HAST) at 135 C/85% RH/5V bias, about 40% failure is observed in 96 hours for such structures.
U.S. Pat. No. 7,235,844 (Itou), the disclosure of which is incorporated herein by reference, discloses that covering the electroplated Cu/Ni/Au interconnect lines with a thick layer of polyimide does not prevent the copper migration from the sidewalls. Itou teaches to first form the TiW/Cu interconnect traces and then coat it with a barrier and aluminum layers on top and sides, followed by photolithography to remove the barrier and the aluminum between the traces. The atmospheric corrosion of aluminum is well known; as is standard practice in IC processing, Itou protects the aluminum coated copper traces from environmental effect by a polyimide passivation. Another photolithography process step is applied to open the bond pad areas. Wire is then bonded on aluminum coated copper pads through the openings in the polyimide. Whereas Itou's method could provide sidewall protection to copper traces, it requires additional expensive photolithography process steps. Furthermore, the wedge wire bonding required for large diameter aluminum wire bonding is not possible because the travel of the wire bond head will impact the polyimide sidewall unless very wide openings in the polyimide are provided, thus constraining the number of Input/Output contacts allowed.
U.S. Pat. No. 6,472,304 (Chittipeddi et al.), the disclosure of which is incorporated herein by reference, discloses the protection of a copper sidewall by Tantalum. However this method requires the Damascene method to form the copper traces. Apart from being an expensive process, the Damascene method is not applicable to thick metal interconnect, as there is no practical way to etch deep trenches in the oxide layer before the pattern defining resist is eroded away. Wire-bonding through openings in polyimide is also required in the structure taught by Chittipeddi et al. thus limiting its application as discussed earlier.
U.S. Pat. No. 6,066,877 (Williams et al.), the disclosure of which is incorporated herein by reference, discloses the plating of a nickel layer on top of aluminum IC interconnects by an electroless plating method. With the high tensile intrinsic thin film stresses in electrolessly plated nickel films, 1×10−10 to 5×10−10 dynes/cm2, the force in the film, stress×thickness, acting normal to the substrate builds up with the film thickness, causing metal film peeling. It is well established that about 5 um is the maximum nickel thickness, as above which nickel film peeling is frequently observed. For reliably safe processing, the electroless nickel film thickness is usually limited to 3 um.
Accordingly, bearing in mind the problems and deficiencies of the prior art, a need for an improved power metal stack in power devices exists.